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FEDL671000-02
1 Semiconductor ML671000
GENERAL DESCRIPTION
This version: Jul. 2001 Previous version: Jul. 2001
OKI's CMOS 32-Bit Single-Chip Microcontroller with Built-in USB Device Controller
The ML671000 is a high-performance CMOS 32-bit microcontroller combining a RISC based, 32-bit CPU core the ARM7TDMITM - with USB device controller, memory and peripherals. The built-in USB device controller which is based on USB1.1 Full-speed (12 Mbps) makes interface with PCs or other devices by USB. The ML671000, which provides the 32-bit data processing capability and built-in peripheral functions performed by UART, serial ports, 16-bit timers, a DMA controller, and a memory controller, is a single-chip microcontroller idealy suited to PC peripheral equipment and communication terminal control applications.
FEATURES (1)
RISC 32-bit CPU (ARM7TDMI) Executable 32-bit instructions and 16-bit instructions General registers: 32-bit x 31 registers Built-in multiplier Little-endian format Internal RAM : 4K bytes External ROM, RAM, I/O : 26M bytes External DRAM : 32M bytes I/O pins: 64 pins (I/O directions are specified at the bit level) 16-bit flexible timer x 2ch (auto-reload, compare-output, PWM, capture modes) 16-bit auto-reload timer x 2ch 12-bit watchdog timer UART (16550A equivalent) x 1ch, UART/synchronous serial x 1ch USB1.1 compliant, support full-speed (12 Mbps) Transmission type: control, bulk, isochronous, interrupt Remote wakeup function Adaptable to USB bus powered devices Four endpoint addresses Endpoint FIFO size EP0 64 bytes x 2 (transmit/receive) EP1 64 bytes x 1 (transmit-receive) EP2 64 bytes x 2 (transmit-receive, 2 levels) EP3 256 bytes x 2 (transmit-receive, 2 levels) x 2ch Single and Dual addressing modes Cycle steal and Burst transfers 8- or 16-bit data transfers Maximum transferring: 65536 times Addressing area: 64M bytes
CPU
Memory Spaces I/O Ports Timers Serial Ports
USB Device Controller
DMA Controller
ARM7TDMI and the ARM POWERED logo are registered trademarks of ARM Ltd., UK. The information contained herein can change without notice owing to the product being under development.
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FEATURES (2)
Interrupt Controller Interrupt sources: 22 (13 internal , 9 external ) Interrupt priority: 8 levels Direct connection to ROM, SRAM, DRAM and I/O. 4-bank memory control ROM, RAM, I/O x 2 banks; DRAM x 2 banks Access wait control parameters for each bank. Arbitration of external bus request Power saving functions Standby modes: HALT and STOP modes Clock gears: Selection of 1/2 OSC, 1/1 OSC, OSC x2 Onboard debugging is possible with JTAG interface. Built-in PLL: x4 3.0 to 3.6 V CPU: 6, 12, 24 MHz; USB: 48 MHz @12 MHz (Operating USBC) CPU: 4 to 24 MHz (Non-Operating USBC) -10C to +70C 128-pin plastic QFP (QFP128-P-1420-0.50-K)
Memory Controller
Other
Power Supply Voltage Operating Frequency Operating Temperature Range Package
APPLICATIONS
Digital still camera, Printer, Terminal Adapter for PC peripherals and Communication terminals.
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BLOCK DIAGRAM
nRST nEA DBSEL TEST TMS nTRST TDI TCK TDO
ARM7DTMI RAM
P0[7:0]/XA[23:16] XA[15:1] XA0/nLB XD[15:0] nR/W nCS0 nRD nWRE/nWRL P1.7/nXWAIT P1.6/nCS1 P1.5/nHB/nWRH P1.4/nRAS1 P1.3/nWH/nCASH P1.2/nRAS0 P1.1/nCAS/nCASL P1.0/nWL/nWE P6.7/nBACK P6.6/nBREQ
VDD VSS
32-bit Core Address Bus
32-bit Core Address Bus
Internal Bus/External Memory Controller
P6.5/DACK1 P6.4/DACK0 P6.3/nDREQ1 P6.2/nDREQ0 P5.7/ DTR P5.6/ RTS P5.5/ CTS P5.4/ DSR P5.3/ DCD P5.2/ RI P5.1/OUT1 P5.0/OUT2 P4.7/SOUT P4.6/ SIN P4.5/TXD0 P4.4/RXD0 P4.3/ TXC P4.2/ RXC
nEFIQ 2-channel DMAC Interrupt Controller P2[7:0]/nEIR[7:0]
UART Port
Bus (16 bits)
Time Base Generator
Peripheral Address Bus
Serial Port
Peripheral Address
Flexible Timer/ Auto-reload Timer (two each)
P3.7/TMCLK3 P3.6/TMCLK2 P3.5/TMCLK1 P3.4/TMCLK0 P3.3/TMIN1/TMOUT1 P3.2/TMIN0/TMOUT0
USB Device Controller
D+ D-
I/O Port
PLL
OSC0 OSC1 CLKOUT PLLEN OSCVDD OSCVSS
P7[7:0]
P6[7:0]*
P4[7:0]*
P3[7:0]*
P2[7:0]*
P1[7:0]*
P5[7:0]*
P0[7:0]* Asterisks indicate pins with secondary functions.
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PIN CONFIGURATION (TOP VIEW)
nEFIQ nRST nTRST TDO TDI TMS TCK TEST P6.0 P6.1 P6.2/nDREQ0 P6.3/nDREQ1 P6.4/DACK0 P6.5/DACK1 P6.6/nBREQ P6.7/nBACK VSS VDD P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
128-Pin Plastic QFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
XA0/nLB XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XA9 XA10 XA11 XA12 XA13 XA14 XA15 P0.0/XA16 P0.1/XA17 P0.2/XA18 P0.3/XA19 P0.4/XA20 P0.5/XA21 P0.6/XA22 P0.7/XA23 VSS VDD XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 XD8 XD9 XD10 XD11 P5.7/DTR P5.6/RTS P5.5/CTS P5.4/DSR P5.3/DCD P5.2/RI P5.1/OUT2 P5.0/OUT1 VDD VSS P4.7/SOUT P4.6/SIN P4.5/TXD P4.4/RXD P4.3/TXC P4.2/RXC P4.1 P4.0 P3.7/TMCLK3 P3.6/TMCLK2 P3.5/TMCLK1 P3.4/TMCLK0 P3.3/TMIN1/TMOUT1 P3.2/TMIN0/TMOUT0 P3.1 P3.0 VDD VSS P2.7/nEIR7 P2.6/nEIR6 P2.5/nEIR5 P2.4/nEIR4 P2.3/nEIR3 P2.2/nEIR2 P2.1/nEIR1 P2.0/nEIR0 PLLEN CLKOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
OSCVSS OSC1 OSC0 OSCVDD nEA DBSEL DD+ VDD VSS P1.7/nXWAIT P1.6/nCS1 P1.5/nHB/nWRH P1.4/nRAS1 P1.3/nWH/nCASH P1.2/nRAS0 P1.1/nCAS/nCASL P1.0/nWL/nWE nWRE/nWRL nRD nCS0 nR/W XD15 XD14 XD13 XD12
FEDL671000-02
ML671000
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PIN DESCRIPTION (1)
Classification
Address Bus Data Bus
Pin Name
XA15 to XA1 nLB/XA0 XD15 to XD0 nCS0 nRD nR/W nWRE/nWRL OSC0 OSC1
I/O
O O I/O O O O O I O O I I I I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O I I/O O I/O O I/O O I/O O I/O O I/O O I/O O
Function
-- -- -- -- -- -- -- -- -- -- -- -- -- Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary
Description
External address bus bits 15 to 1 Bank 0/1 lower byte select or external address bus bit 0 External data bus Bank 0 chip select signal Bank 0/1 read enable signal Read strobe signal Bank 0/1 write enable or lower byte write enable signal Connection pin for crystal oscillator or ceramic resonator If an external clock used, input the clock signal to this pin. Connection pin for crystal oscillator or ceramic resonator If an external clock used, leave this pin open (unconnected). Internal system clock output Enable pin for internal PLL. If PLL is to be used, connect this pin to VDD. Power supply pin for internal oscillator circuit and PLL. Connect to VDD. Power supply pin for internal oscillator circuit and PLL. Connect to GND. Bit 7 of port 0 Bit 23 of external address bus Bit 6 of port 0 Bit 22 of external address bus Bit 5 of port 0 Bit 21 of external address bus Bit 4 of port 0 Bit 20 of external address bus Bit 3 of port 0 Bit 19 of external address bus Bit 2 of port 0 Bit 18 of external address bus Bit 1 of port 0 Bit 17 of external address bus Bit 0 of port 0 Bit 16 of external address bus Bit 7 of port 1 External wait cycle insert input Bit 6 of port 1 Bank 1 chip select signal Bit 5 of port 1 Bank 0/1 upper byte select or upper byte write enable signal Bit 4 of port 1 Bank 3 row address strobe signal Bit 3 of port 1 Bank 2/3 upper byte column address strobe signal. Bit 2 of port 1 Bank 2 row address strobe signal Bit 1 of port 1 Bank 2/3 column address strobe or lower byte column address strobe signal Bit 0 of port 1 Bank 2/3 lower byte write enable or write enable signal
Bus Control
Clock Control
CLKOUT PLLEN OSCVDD OSCVSS P0.7/XA23 P0.6/XA22 P0.5/XA21 P0.4/XA20 P0.3/XA19 P0.2/XA18 P0.1/XA17 P0.0/XA16
I/O Ports
P1.7/nXWAIT P1.6/nCS1 P1.5/nHB/ nWRH P1.4/nRAS1 P1.3/ nWH/nCASH P1.2/nRAS0 P1.1/ nCAS/nCASL P1.0/ nWL/nWE
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PIN DESCRIPTION (2)
Classification Pin Name
P2.7/nEIR7 P2.6/nEIR6 P2.5/nEIR5 P2.4/nEIR4 P2.3/nEIR3 P2.2/nEIR2 P2.1/nEIR1 P2.0/nEIR0 P3.7/TMCLK3 P3.6/TMCLK2 P3.5/TMCLK1 I/O Ports P3.4/TMCLK0 P3.3/ TMIN1/ TMOUT1 P3.2/ TMIN1/ TMOUT0 P3.1 P3.0 P4.7/SOUT P4.6/SIN P4.5/TXD P4.4/RXD P4.3/TXC P4.2/RXC P4.1 P4.0
I/O
I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I/O I/O I/O I/O I/O I/O O I/O I I/O O I/O I I/O I/O I/O I/O
Function
Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary -- -- Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary -- --
Description
Bit 7 of port 2 External interrupt request 7 input pin Bit 6 of port 2 External interrupt request 6 input pin Bit 5 of port 2 External interrupt request 5 input pin Bit 4 of port 2 External interrupt request 4 input pin Bit 3 of port 2 External interrupt request 3 input pin Bit 2 of port 2 External interrupt request 2 input pin Bit 1 of port 2 External interrupt request 1 input pin Bit 0 of port 2 External interrupt request 0 input pin Bit 7 of port 3 External clock input pin for timer 3 Bit 6 of port 3 External clock input pin for timer 2 Bit 5 of port 3 External clock input pin for timer 1 Bit 4 of port 3 External clock input pin for timer 0 Bit 3 of port 3 If timer 1 is set to the compare-output or PWM modes, this pin is an output. If set to the capture mode, this pin is an input. Bit 2 of port 3 If timer 0 is set to the compare-output or PWM modes, this pin is an output. If set to the capture mode, this pin is an input. Bit 1 of port 3 Bit 0 of port 3 Bit 7 of port 4 Serial data output pin for UART serial port Bit 6 of port 4 Serial data input pin for UART serial port Bit 5 of port 4 Transmit data output pin for UART/synchronous serial port Bit 4 of port 4 Receive data input pin for UART/synchronous serial port Bit 3 of port 4 Transmit clock I/O pin for UART/synchronous serial port Bit 2 of port 4 Receive clock I/O pin for UART/synchronous serial port Bit 1 of port 4 Bit 0 of port 4
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PIN DESCRIPTION (3)
Classification Pin Name
P5.7/DTR P5.6/RTS P5.5/CTS P5.4/DSR P5.3/DCD P5.2/RI P5.1/OUT1 P5.0/OUT2 P6.7/nBACK I/O Ports P6.6/nBREQ P6.5/DACK1 P6.4/DACK0 P6.3/nDREQ1 P6.2/nDREQ0 P6.1 P6.0 P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0 D+ D- TCK TMS TDI TDO nTRST nEFIQ nEA nRST DBSEL TEST Power Supply VDD VSS
I/O
I/O O I/O O I/O I I/O I I/O I I/O I I/O O I/O O I/O O I/O I I/O O I/O O I/O I I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I O I I I I I I I I
Function
Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Description
Bit 7 of port 5 DTR signal output pin for UART serial port Bit 6 of port 5 RTS signal output pin for UART serial port Bit 5 of port 5 CTS signal input pin for UART serial port Bit 4 of port 5 DSR signal input pin for UART serial port Bit 3 of port 5 DCD signal input pin for UART serial port Bit 2 of port 5 RI signal input pin for UART serial port Bit 1 of port 5 OUT1 signal output pin for UART serial port Bit 0 of port 5 OUT2 signal output pin for UART serial port Bit 7 of port 6 Bus release request acknowledged signal output pin Bit 6 of port 6 Bus release request signal input pin Bit 5 of port 6 Data transfer request 1 acknowledged signal output pin Bit 4 of port 6 Data transfer request 0 acknowledged signal output pin Bit 3 of port 6 Data transfer request 1 signal input pin Bit 2 of port 6 Data transfer request 0 signal input pin Bit 1 of port 6 Bit 0 of port 6 Bit 7 of port 7 Bit 6 of port 7 Bit 5 of port 7 Bit 4 of port 7 Bit 3 of port 7 Bit 2 of port 7 Bit 1 of port 7 Bit 0 of port 7 USB data I/O pins Test clock input pin Test mode select pin Test data input pin Test data output pin Boundary scan logic reset input pin External FIQ (high-speed interrupt) interrupt request signal input pin Normally connected to ground System reset signal input pin for this LSI device During a system reset of this LSI device, this pin sets the bank 0 data bus width. To set a 16-bit bus width, connect to VDD. To set an 8-bit bus width, connect to GND. This pin sets the test and debug modes for this LSI device. Normally connected to GND. Power supply pin. Connect all VDD pins to the power supply. Ground pin. Connect all VSS pins to GND.
USB Port
Debug Interface Interrupt System Control
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OVERVIEW OF INTERNAL PERIPHERAL FUNCTIONS
I/O Ports The 64 I/O ports are configured from the 8-bit ports P0 to P7. Each bit of each port can be specified as an input or output. If specified as an input, the port becomes a high impedance input. In addition to their port function (primary function), some ports are assigned secondary functions such as an external interface function or an I/O pin for an internal peripheral. Timers The timers consist of a 2-channel 16-bit flexible timer and a 2-channel 16-bit general-purpose timer. A count clock can be selected for each channel. - Flexible timer Operating modes: auto-reload timer, compare-output, PWM, capture - General-purpose timer Auto-reload timer - Synchronous timer operation Timer channel can be started and stopped in union. - Count clock A count clock can be selected for each timer as: 1/1, 1/2, 1/4, 1/8, 1/16, and 1/32 of the system clock, or as an external clock. Time Base Generator The time base generator consists of the time base counter, which drives frequency dividers deriving the time base signals for on-chip peripherals from the system clock signals, and a watchdog timer, which counts time base clock cycles and produces a system reset signal when its internal counter overflows. UART Serial Port Functionally the same as the 16550A, the UART serial port is equipped with 16-byte FIFOs for both receive and transmit, modem control signals, a dedicated baud rate generator, etc. - Full duplex operation - Independent controls for transmit, receive, line status and data set interrupt - Modem control signals: CTS, DSR, DCD, DTR, RTS and RI - Built-in dedicated baud rate generator - Data length:5, 6, 7, or 8 bits - Stop bit: 1, 1.5, or 2 bits - Parity: odd, even, or none - Detection of receive errors: parity error, framing error, overrun error, or data error of break interrupt
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UART/Synchronous Serial Port The UART/synchronous serial port is a serial port that operates in two communication modes, the UART mode and synchronous mode. In the UART mode, characters units are synchronized according to the controlled start bit and stop bit, and data is transferred. In the synchronous mode, the data transfer is synchronized to the controlled shift clock. - Built-in dedicated baud rate generator - Data length:7 or 8 bits - Stop bit: 1 or 2 bits (UART mode only) - Parity: even or odd parity (none in the synchronous mode) - Detection of receive errors: parity error, framing error, and overrun error (only overrun error in the synchronous mode) - Full-duplex operation Interrupt Controller The interrupt controller manages interrupt requests from 9 external sources and 13 internal sources, and passes them on to the CPU as interrupt request (IRQ) or fast interrupt request (FIQ) exception requests. An interrupt level can be set for each interrupt and priority can be controlled. - Supports 9 external interrupt sources from nEFIQ and nEIR [7:0] pins and 13 internal interrupt sources from internal peripherals such as the USB device controller and the timers. - To simplify the control of interrupt priority, 8 interrupt levels can be set for each interrupt source. - The interrupt controller assigns a unique interrupt number to each interrupt source to permit rapid branching to the appropriate routine. Direct Memory Access (DMA) Controller The direct memory access (DMA) controller is used instead of the CPU to transfer data between internal memory, internal peripherals, external memory and memory mapped external devices. - Built-in 2 channels - Supports 64MB address area - Transfer data size: 8 or 16 bits - Maximum transferring: 65536 times - Addressing modes: single or dual address mode - Bus modes: cycle-steal or burst mode - Supports transfer requests from nDREQ[0:1] pins, internal peripheral devices and software. - Generates transfer complete interrupt requests when transfer is completed.
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Universal Serial Bus (USB) Device Controller The USB device controller consists of a protocol engine to control the USB communications protocol, DPLL, status/control, FIFO control, a USB transceiver, etc. The USB device controller conforms to USB spec. 1.1 full-speed (12Mbps) . - Supports the 4 types of transfers that are specified by the USB standard. (control transfer, bulk transfer, isochronous transfer, and interrupt transfer) - Remote wakeup function - Adaptable to USB bus powered devices - 4 endpoint addresses Endpoint FIFO contents and functions
Endpoint EP0 EP1 EP2 EP3 64 bytes 64 bytes 64 bytes 64 bytes 256 bytes FIFO contents x 1 (transmit) x 1 (receive) x 1 (transmit-receive) x 2 (transmit-receive) x 2 (transmit-receive) Control Bulk, interrupt Bulk, interrupt, isochronous Bulk, interrupt, isochronous Transfer mode
External Memory Controller The external memory controller generates control signals for accessing external memory (ROM, RAM, DRAM, etc.) and peripheral devices mapped in the external memory space, and arbitrates external bus requests from external devices. - Manages memory by dividing the memory space into 4 banks * 2 banks of ROM, SRAM, and I/O * 2 banks of DRAM * Each bank has a 16MB address space. * Bus width (8 or 16 bits) and wait cycles can be specified for each bank. - ROM, SRAM and I/O can be connected directly. Outputs a strobe signal for the ROM, SRAM and I/O. - DRAM can be connected directly. * Row and column addresses are output as multiplexed signals. * Random access mode or high-speed page mode * Supports CAS before RAS refresh and self-refresh. Clock Control The clock controller generates and controls the system clock based on the internal oscillator circuit and phase locked loop (PLL). It also controls the transitions to and from standby modes (HALT and STOP modes) and returns to normal operation of mode. - It offers a choice of divider ratio for adjusting operating clock frequency to match the load processing. When using PLL: 2 x f, f, f/2 Not using PLL: f, f/2, f/4, f/8 f = input clock frequency
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage Input voltage Output current Power dissipation Storage temperature Symbol VDD VIN IO PD TSTG Condition VDD GND = 0 V Ta = 25C -- Rated value -0.3 to +4.6 -0.3 to VDD +0.3 12 1 -55 to +150 Unit V mA W C
RECOMMENDED OPERATING CONDITIONS
Parameter Supply voltage Storage holding voltage Operating frequency Ambient temperature Symbol VDD VDDH fC Ta Condition -- fC = 0 Hz VDD = 3.0 to 3.6 -- Min. 3.0 2.0 4 -10 Typ. 3.3 -- -- 25 Max. 3.6 3.6 24 +70 (GND = 0 V) Unit V MHz C
Input Clock Conditions Connecting a crystal oscillator
PLLEN Pin "H" Level "L" Level Input frequency 6 to 12 MHz 4 to 12 MHz Operating frequency (fC) 12 to 24 MHz 4 to 12 MHz
Using an external clock supply
PLLEN Pin "H" Level "L" Level Input frequency 6 to 12 MHz 4 to 48 MHz Operating frequency (fC) 12 to 24 MHz 4 to 24 MHz
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ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
Parameter H-level input voltage H-level input voltage H-level input voltage L-level input voltage L-level input voltage H-level output voltage L-level output voltage Input leakage current Output leakage current H-level input current 3 Symbol VIH1 VIH2 VIH3 VIL1 VIL2 VOH VOL |ILI| |ILO| IIH Condition -- -- -- -- -- IOH = -4 mA IOH = -100 A IOL = 4 mA VI = 0/VDD VO = 0/VDD VI = VDD Pull-down resistor 50k VI = 0 V Pull-up resistor 50k -- -- -- (*3) (*4) fC = 24 MHz No load (VDD = 3.0 to 3.6 V, GND = 0 V, Ta= -10 to +70C) Min. Typ. (*1) Max. Unit -- 5.5 0.76 x VDD 0.76 x VDD 2.0 -0.3 -0.3 2.2 VDD-0.2 -- -- -- 20 -- -- -- -- -- -- 66 VDD+0.3 5.5 0.2 x VDD 0.8 -- -- 0.4 1.0 (*2) 1.0 (*2) 200
A
1 2, 3 4 1, 2, 3 4
V
L-level input current Input pin capacitance Output pin capacitance I/O pin capacitance Current consumption (in STOP mode) Current consumption (in HALT mode) Current consumption (during operation)
2
IIL CI CO CIO IDDS IDDH IDD
-200 -- -- -- -- -- -- --
-60 6 9 10 3 20 35 70
-20 -- -- -- 150 500 50 mA 105
pF
A
1. Applied to PIO7 to PIO0, nEFIQ, nEA, DBSEL, TEST, and PLLEN 2. Applied to nRST, TDI, TMS, and TCK 3. Applied to nTRST 4. Applied to XD0 to XD15 (*1): Typ. indicates values for the case where VDD = 3.3 V and Ta = 25C. (*2): 50 A when Ta is 50C or above. (*3): Ta = -10 to +50C (*4): Ta = +50 to +70C
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DC Characteristics (2)
Parameter Differential input sensitivity
USB Port (D+, D-)
Symbol VDI VCM VSE VOH VOL ILO Condition {(D+)-(D-)} Including VDI part -- 15k to GND 15k to 3.6 V 0 VA
Differential common mode range Single ended receiver threshold H-level output voltage L-level output voltage Output leakage current
V
(*1): Typ. indicates values for the case where VDD = 3.3 V and Ta = 25C.
AC Characteristics Clock timing
Parameter Symbol Clock frequency fC Clock cycle time tC Clock H-level pulse width tCH Clock L-level pulse width tCL External clock input frequency fEXC External clock input cycle time tEXC External clock input H-level pulse tEXCH width External clock input L-level pulse tEXCL width Clock rise time tR Clock fall time tF External clock input rise time tEXR External clock input fall time tEXF Condition (VDD = 3.0 to 3.6 V, GND = 0 V, Ta = -10 to +70C) Min. Typ. Max. Unit 4 -- 24 MHz 42 -- 250 ns 15 -- -- 15 -- -- 4 -- 24 MHz = 3.0 to 3.6 V 42 -- 250 15 15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 5 5 5 ns
VDD
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Control signal timing
Parameter nRST pulse width (*1) nRST pulse width (*2) nEFIQ pulse width nEIR pulse width TMIN pulse width TMCLK pulse width TCX, RXC frequency TXC, RXC H-level pulse width TXC, RXC L-level pulse width TXD delay time RXD setup time RXD hold time nDREQ0, nDREQ1 setup time nDREQ0, nDREQ1 hold time DACK0, DACK1 delay time Symbol tRSTW1 tRSTW2 tEFIQW tEIRW tTMINW tTMCLKW fSC tSCLKH tSCLKL tTXD tRXS tRXH tREQS tREQH tDACKD Condition -- -- -- -- -- -- -- -- -- CL = 50 pF -- -- -- -- CL = 50 pF (VDD = 3.0 to 3.6 V, GND = 0 V, Ta = -10 to +70C) Min. Typ. Max. Unit 2 tC -- -- ns Oscillation stabilization -- -- -- time 2 tC -- -- 2 tC -- -- ns 2 tC -- -- 2 tC -- -- -- -- 1/4 fC MHz 2 tC -- -- 2 tC -- -- -- -- 1 tC+22 0.5 tC 1.5 tC 1.0 2.6 2.4 -- -- -- -- -- -- -- -- -- 15.2 ns
(1*): Not including when power is turned on and during STOP mode (2*): When power is turned on and also during STOP mode
External bus timing
Parameter XA[23:1], nLB/XA0 delay time XD[15:0] output delay time XD[15:0] output hold time XD[15:0] input setup time XD[15:0] input hold time nXWAIT setup time nXWAIT hold time nHB delay time nCS[1:0] delay time nWRE, nWRH, nWRL delay time nRD assert delay time nR/W assert delay time nRAS[1:0] assert delay time nCAS assert delay time nWE, nWH, nWL assert delay time nBREQ setup time nBREQ hold time nBACK delay time High impedance delay time Symbol tXAD tXDOD tXDOH tXDIS tXDIH tXWAITS tXWAITH tHBD tCSD tWRD tRDD tR/WD tRASD tCASD tWED tBREQS tBREQH tBACKD tXHD (VDD = 3.0 to 3.6 V, GND = 0 V, Ta = -10 to +70C) Condition Min. Typ. Max. Unit 0 -- 12 2 -- 18 9 -- -- 12 0 0 0 0 0 0 0 0 1 1 1 11 0 2 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9 10 9 8 10 10 10 12 -- -- 13 12
CL = 50 pF
ns
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TIMING DIAGRAMS
Clock Timing
tCH tC tCL tR tF
CLKOUT
tEXCH
tEXC
tEXCL
tEXR
tEXF
External clock Input
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Control Signal Timing
tRSTW1 , tRSTW2 nRST
tEFIQW, tEIRW
nEFIQ, nEIR
tTMINW TMIN
tTMCLKW TMCLK
tTMCLKW
tSCLKH
tSCLKL
TXC, RXC tTXDH
TXD tRXDS tRXDH
RXD
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DMA Timing
CLKOUT
tREQS
tREQH
nDREQ0, nDREQ1
tDACKD
DACK0, DACK1
nXWAIT Signal Input Timing
CLKOUT
tXWAITS
tXWAITH
nXWAIT
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FEDL671000-02
1 Semiconductor
ML671000
External Bus Release Timing
CLKOUT
tXWAITS
tXWAITH
nBREQ
tBACKD
tBACKD
nBACK
tXHD XA, XD Control signals
tXHD
18/25
FEDL671000-02
1 Semiconductor
ML671000
External Bus Timing
Bank 0, 1 write cycle
Write Cycle
CLKOUT
tXAD XA[23:1] nLB/XA0
tHBD
nHB
tCSD
nCS[1:0]
tWRD nWRE nWRH, nWRL
tWRD
tR/WD
nR/W
tXDOD
tXDOH
XD
19/25
FEDL671000-02
1 Semiconductor
ML671000
Bank 0, 1 read cycle Read Cycle
CLKOUT
tXAD XA[23:1] nLB/XA0
tHBD
nHB
tCSD
nCS[1:0]
tRDD
tRDD
nRD
tR/WD
nR/W
tXDIS
tXDIH
XD
20/25
FEDL671000-02
1 Semiconductor
ML671000
Bank 2, 3 write cycle
W rite Cycle
CLKOUT
t XAD
XA[23:1] nLB/XA0
t R ASD
t R ASD
nRAS[1:0]
t C ASD
t C ASD
nCAS[1:0]
t W ED
t W ED
nWE nWH, nWL
t XD O D
t XD O D
XD
nR/W
21/25
FEDL671000-02
1 Semiconductor
Bank 2, 3 read cycle
Read Cycle
ML671000
CLKOUT
t XAD
XA[23:1] nLB/XA0
t R ASD
t R ASD
nRAS[1:0]
t C ASD
t C ASD
nCAS[1:0]
t XD IS
t XD IH
XD
nR/W
22/25
FEDL671000-02
1 Semiconductor
CAS before RAS (CBR) refresh
ML671000
CLKOUT
tR A SD tR A SD
nRAS
tC A SD tC A SD
nCAS
Self-refresh
CLKOUT
tR A SD tRASD
nRAS
tC A SD tC A SD
nCAS
23/25
FEDL671000-02
1 Semiconductor
ML671000
PACKAGE DIMENSIONS
(Unit: mm)
QFP128-P-1420-0.50-K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 1.19 TYP. 4/Nov. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
24/25
FEDL671000-02
1 Semiconductor
ML671000
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-todate. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd.
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